"DSP Builder version 2.0 provides significant benefits to DSP engineers, making it extremely easy for them to use programmable logic for their designs." "Altera's DSP Builder continues to push the true capabilities of programmable logic for a variety of emerging high-performance DSP applications," said Ken Karnofsky, director of DSP and Communications at The MathWorks.
These features allow Altera's DSP Builder tool to facilitate a sophisticated system-level integration and enable designers to implement their own customized logic.
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OpenCore Plus IP cores currently available with DSP Builder version 2.0 include a Viterbi compiler, constellation mapper/demapper, Reed-Solomon compiler, numerically controlled oscillator (NCO), fast Fourier transform (FFT), infinite impulse response (IIR), and symbol interleaver/deinterleaver. DSP Builder even provided the option to synthesize and compile the generated VHDL files automatically, providing us with an ideal platform to design, simulate, synthesize, and compile a complex design and immediately test it on a board."Īdditional features of DSP Builder version 2.0 include Altera's OpenCore ® Plus free test drive DSP IP cores and support for black-box components. "We were able to use the MATLAB and Simulink tools together with the logic blocks found in Altera's DSP Builder to design the equalizer as a Simulink model, simulate it in MATLAB, and then convert it to HDL. "Using DSP Builder for our next-generation equalizer and error correction schemes significantly reduced the amount of time required to evaluate and prove the design," said Pinar Ormeci, design engineer at Narad Networks. The SOPC Builder interface allows the user to build systems that incorporate Simulink designs, Altera Nios ® embedded processors and IP cores. The new version also gives designers an interface to SOPC Builder, Altera's system generation tool for the development of system-on-a-programmable-chip (SOPC) applications. With the new interface, DSP designers can probe the internal nodes of the DSP development board from The MathWorks' MATLAB workspace. In addition to supporting the Stratix device family, this new version of DSP Builder includes an interface to the Quartus II design software's SignalTap ® embedded logic analyzer. With DSP Builder, designers can automatically generate pre-verified RTL output files-including an RTL design and testbench-from the Simulink software. The DSP Builder tool provides a seamless design flow in which designers perform algorithmic design and system-level integration in The MathWorks' MATLAB and Simulink software, respectively, then port the design to HDL for use in Altera's Quartus ® II design software. An intuitive design tool that simplifies the development of digital signal processing (DSP) systems targeted for Altera-s programmable logic devices (PLDs), Altera-s DSP Builder tool allows DSP designers to realize immediately the benefits of programmable logic without having to learn new design flows or programming languages.
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San Jose, Calif., J- Altera Corporation (NASDAQ: ALTR) today announced the availability of DSP Builder version 2.0, a major enhancement of its DSP design tool that adds support for the high-performance Stratix ™ device family as well as new hardware verification and intellectual property (IP) integration features. Altera's DSP Builder Tool Supports Stratix Devices, Eases Migration to Programmable Logic